Integrated semiconductor circuits, particularly arrays having transistors each of which represents a binary digit of information, as in read only memories (ROM), have achieved high device or cell densities.
In, e.g., U.S. Pat. No. 3,914,855, filed May 9, 1974, there is described a read only memory wherein the array has transistors made with a thin gate dielectric exhibiting a low threshold voltage for storing one digit of binary information and transistors made of a thick gate dielectric exhibiting a considerably higher threshold voltage for storing the other digit of binary information. This patent also describes a read only memory wherein the array is encoded by etching apertures in the gate electrodes of selected devices and implanting ion impurities through the apertures to render the selected devices inoperative, thus defining one digit of binary information, while the remaining devices which do not have apertures in the gate electrode are operative devices or transistors defining the other digit of binary information. The read only memories employing the thick and thin gate dielectrics have a high cell density but the personalization of the memory cells must be made during the early steps of the process, whereas the read only memories having apertures in the gate electrodes require a relatively wide gate electrode or word line and, therefore, sacrifice density.
U.S. Pat. No. 4,059,825, filed Dec. 29, 1975, discloses a read only memory wherein selected transistors forming the memory cells storing one digit of information are programmed by an ion implant step which produces in these transistors a threshold voltage of about zero to permanently turn on these transistors. The other digit of binary information is represented by transistors which do not have this ion implant and, therefore, having a higher threshold voltage. The programming of this memory occurs during the early steps of the process prior to forming the gate electrodes of the transistors.
A read only memory disclosed in U.S. Pat. No. 4,096,522, filed Aug. 8, 1977, is personalized at a relatively late stage during the processing thereof by completing connections between the source and drain electrodes and the channel region of the transistors after the gate electrodes of the transistors have been formed. However, this process sacrifices density since a gap or space must be provided near each gate electrode to complete by ion implantation the source and drain electrodes on the transistors selected for storing one digit of binary information while that gap or space serves as an open circuit in transistors selected for storing the other digit of binary information.
U.S. Pat. No. 4,045,811, filed Aug. 4, 1975, describes a read only memory wherein selected transistors are made non-operative or with a high threshold by providing diffused regions under the gate electrodes in the channel regions which serve to raise the value of the threshold voltage of these transistors above a voltage value normally applied to the gate electrodes of the transistors during the operation of the memory. These diffused regions are formed in the channel regions during a relatively early step in the process and prior to forming the gate electrodes.
In U.S. Pat. No. 4,161,039, filed FEB. 6, 1978, there is disclosed a memory array utilizing field effect transistors wherein information is stored in floating gates and the channel region is made short by employing double-diffusion processing techniques, as disclosed in more detail in "Electronics", Feb. 15, 1971, at pages 99-104. This memory is not a simple read only memory but it can be reprogrammed by erasing the stored information with ultraviolet light.